Professor, Department of Computer Science & Engineering
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Conference Papers Published (5)
Title of the paper Conference Year Role Vol Number-Page Name

Synthesis of Symmetric Boolean Functions Using a Three-Stage Network Proc. of International Symposium on Electronic System Design (ISED) 2014 A. Deb, D. K. Das, and B. B. Bhattacharya -182-186
A Regular Network of Symmetric Functions in Quantum-Dot Cellular Automata Proc. of International Symposium on VLSI Design and Test (VDAT) 2014 A. Deb and D. K. Das -1-6
Modular Design for Symmetric Functions Using Quantum Quaternary Logic Proc. of International Symposium on Electronic System Design (ISED) 2013 A. Deb, D. K. Das, and S. Sur-kolay -143-147
Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure Proc. of Reversible Computation (RC) 2013 A. Deb, D. K. Das, H. Rahaman, B. B. Bhattacharya, R. Wille, and R. Drechsler -182-195
Reversible Synthesis of Symmetric Boolean Functions based on Unate Decomposition Proc. of ACM Great Lakes Symposium on VLSI (GLSVLSI) 2013 A. Deb, D. K. Das, H. Rahaman, and B. B. Bhattacharya -351-352
Journal Papers Published (18)
Title of the paper Journal of publication Year Role Vol Number-Page Name

An iterative structure for synthesizing symmetric functions using quantum-dot cellular automata Microprocessors and Microsystems 2017 Arighna Deb and Debesh K Das 53-157-167
A New Squarer Design with Reduced Area and Delay IET Computers and Digital Techniques 2016 Arindam Banerjee and Debesh K. Das vol. 10 no. 5-205-214
Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability ACM Journal on Emerging Technologies in Computing Systems (JETC) 2016 A. Deb, D. K. Das, H. Rahaman, R. Wille, R. Drechsler, B. B. Bhattacharya vol. 12 (4)-34:1-34:29
The design of reversible signed multiplier using ancient Indian mathematics Journal of Low Power Electronics 2015 Arindam Banerjee and Debesh K. Das vol. 11, no. 4-467-478
One More Class of Sequential Circuits having Combinational Test Generation Complexity Journal of Electronic Testing: Theory and Applications 2015 Debesh K Das and Hideo Fujiwara vol. 31, issue 3-321-327
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Ph.D. Thesis Guidance (2)
Name Of The Scholar Title Of The Thesis Co-Superviser Status Year

Debarati Bhunia Chakraborty Debesh Das
Suman Kundu Debesh Kumar Das
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