Professor, Department of Electronics & Telecommunication Engineering
Jadavpur University, Kolkata - 700 032
PH:033-2457-2813
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Degree	Year	University
Ph.D. 2010 IIT Kharagpur M.Tech 2001 University of Calcutta B.Tech 1999 University of Calcutta

Name Of The Institution Position Held Period Jadavpur University Professor 2020, November 23 to Till Date Jadavpur University Associate Professor 2017, November 23 to 2020, November 22 Haldia Institute of Technology Professor 2015, June 1 to 2017, November 22 Haldia Institute of Technology Associate Professor 2011, March 09 to 2015, May 31 Haldia Institute of Technology Senior Lecturer 2006, May 19 to 2006, July 22 More

Communication Engineering

VLSI architecture for Error Correcting Codes, Finite Field Arithmetic Circuits and Cryptographic Algorithms

As on January 2018: Teaching Experience: 11.8 Years Research Experience: 11.5 Years

Title of the paper Conference Year Role Vol Number-Page Name Designing of Sharp Transition Low Pass FIR Filter using Multistage FRM Approach 2nd Int. conf. on Devices for Integrated Circuit (DevIC 2017), India 2017 -414-418 Area Optimized SEC-DED Codec for Computer Memory 5th Int. Conf. on Computing, Communication and Sensor Network, (CCSN2016), India 2016 -159-163 A Symmetric Key Based Image Encryption Scheme Int. Conference on Computing and Communication Systems(I3CS 2016), India 2016 First Author - New Hybrid CA Rule Sets for Cryptographic Design Int. conf. on Computer, Communication, Control and Information Technology, India 2015 -1-5 Compact RS(32, 28) Encoder 1st Int. Conf. on Intelligent Computing & Applications(ICICA), India 2015 -89-95 More

Title of the paper Journal of publication Year Role Vol Number-Page Name FPGA based Area Efficient RS (23, 17) Codec Journal of Microsystem Technologies, Springer 2017 vol. 23, no. 3-639-650 Compact CA-based Single Byte Error Correcting Codec IEEE Transactions on Computers 2017 Second author DOI: 10.1109/TC.2017.2739726- CA-based Area Optimized Three Bytes Error Detecting Codes Journal of Cellular Automata, Old City Publishing 2015 vol. 10, no. 5-6-409-423 A modified Karatsuba multiplier for key equation solver in RS code Journal of Radioelectronics and Communications Systems, Springer 2015 vol. 58, no. 10-452-461 A Fault Based Attack on MDS-AES International Journal of Network Security 2014 vol.16, no.3-193-198 More

Name Of The Scholar Title Of The Thesis Co-Superviser Status Year Jagannath Samanta (Thesis Submitted) Design and Implementation of Error Correcting Codes Dr. Soma Barman, University of Calcutta Ongoing 2017 Supriyo De Design and Analysis of Schemes for Image Security Ongoing 2015

Name Of The Scholar Title Of The Thesis Co-Superviser Year Tarique Hassan FPGA based implementation of GF(28) multipliers 2016 Nikhil Nag-banshi Low Power Implementation of AES Algorithm 2013 Anindya Sundar Das Design and Implementation of RS Codec 2012 Satyajit Das Design and Implementation of SPN-type Block Cipher 2012

Project Title Worked As Funding Agency Amount Duration Period Status Analysis and Design of SPN-type Block Cipher Principal Investigator SERB, Govt. of India, under Fast Track Young Scientist Scheme Rs. 6,65,000/- 3 Years 2012 to 2015 Complete

Title Organised By Venue Year Design and Analysis of SPN-type Block Cipher Haldia Institute of Technology Haldia 2015 Role of Diffusion Layer in Block Cipher PSG College of Technology Coimbatore 2010

Title Senior Member, IEEE Fellow, Institution of Engineers, India (IEI) Life Member, Cryptology Research Society of India (CRSI)

Program Name Session Title Organised By Venue Year Int. Conference of Computing and Communication Systems (I3CS 2016) Technical session North Eastern Hill University, Shillong Dept. of Information Technology 2016 Back To Top

Served Dept. of ECE, Haldia Institute of Technology, Haldia, West Bengal as a HOD from 01.04.2015 to 20.11.2017 Organized ICCDC 2017 as a Joint Organizing Secretary & ICMC 2015, NCACD 2012 and NCACD2011 as a Convener